In today’s QPU designs, almost 90% of the chip is eaten by signal routing, not qubits. Adding qubits forces denser routing, increases crosstalk, and erodes yield. These issues compound exponentially with every added qubit, which is why the entire industry has been stuck at 100–150 qubits per chip.

If QPUs stay small, a last resort for scaling is stitching together many cryostats over lossy and low-bandwidth links. With today’s QPU sizes, that would require a datacenter full of fridges just to get modest compute. Without hyperscaling QPUs, networking alone will never deliver economically relevant systems.

VIO scales modularly while still functioning as one unified qubit plane, because high-fidelity chip-to-chip links seamlessly connect the edge qubits of each chip. This is possible because vertical signal delivery frees the chip edges from routing out. The vertical signal delivery happens through a vertical chip stack that also integrates all peripheral components directly into the vertical chips.

With up to 40,000 input-output lines, VIO-40K enables 10,000-qubit QPUs. Its architecture is optimized for high heat-transfer capacity, allowing the heat load of a 10,000-qubit processor to be managed within a single cryostat.